The present invention relates to a semiconductor memory and, more particularly, to a random access memory of a static type having bipolar transistors and complementary MOS transistors.
Utilizing advantages of both a bipolar transistor circuit and a complementary MOS transistor circuit, it was disclosed in NIKKEI ELECTRONICS, Mar. 10, 1986, at page 199 to 217 to construct a static type random access memory by bipolar transistors and CMOS transistors. Such a memory is called "Bi-CMOS" SRAM. In the Bi-CMOS SRAM disclosed, peripheral circuits such as an address buffer, a decoder/driver, a sense amplifier and an output circuit are constructed by Bi-CMOS transistor circuits and a memory cell array is constructed by an N-channel MOS transistor circuit. As a result, an operation speed of each peripheral circuit is improved, while realizing a low power consumption and a high integration.
However, a memory cell array of the Bi-CMOS SRAM is the same as that of a conventional SRAM constructed only by MOS transistors, and therefore an operation speed of the cell array is not improved. More specifically, a great number of memory cells are connected in common to each pair of bit lines. For this reason, these bit lines are prolonged, so that they have a large stray capacitance. One of each pair of bit lines is discharged in accordance with the data stored in a selected memory cell, and the discharging of the bit line is carried out by a MOS transistor contained in the selected memory cell. However, the MOS transistors generally have a relatively low current ability. Moreover, the MOS transistor is formed in a fine pattern to decrease the size of the memory cell. Therefore, the current ability of the MOS transistor in the memory cell is very small, so that the bit line is discharged with a large time constant. As a result, the improvement in the operation speed of the Bi-CMOS SRAM is restricted.